SystemC from scratch

I have been struggling with Verilog and VHDL for more than 15 years. It is time to take a step up on the abstraction ladder. You are welcome to join me, I have decided to learn SystemC.


SystemC is a single, unified design and verification language that expresses architectural and other system-level attributes in the form of open-source C++ classes. It enables design and verification at the system level, independent of any detailed hardware and software implementation, as well as enabling co-verification with RTL design.
This higher level of abstraction enables considerably faster, more productive architectural trade-off analysis, design, and redesign than is possible at the more detailed RT level. Furthermore, verification of system architecture and other system-level attributes is orders of magnitude faster than that at the pin-accurate, timing-accurate RT level.

Read more in my blog